Programmable integrated circuits are a type of integrated circuit that can be configured by a user to implement custom logic functions. In a typical scenario, a logic designer uses computer-aided design (CAD) tools to design a custom logic circuit. When the design process is complete, the CAD tools generate configuration data. The configuration data is loaded into a programmable integrated circuit to configure the device to perform desired logic functions.
In a typical system, a programmable integrated circuit, memory devices, and other electronic components are mounted on a printed circuit board. The programmable integrated circuit includes memory interface circuitry that is used to relay data back and forth between the programmable integrated circuit and the memory devices (i.e., the memory interface circuitry is used to read data from and write data into the memory devices). When performing such memory read and write operations, the timing of control and data signals is critical.
Because programmable integrated circuits can be configured in many different ways and are installed on many different types of boards, the lengths of circuit board traces coupling the programmable integrated circuit to the memory devices can vary from one system to another. As a result, it is generally not possible to know in advance exactly how data and clock paths between a programmable integrated circuit and a given memory device will perform. In some systems, the data and clock paths may have one set of timing characteristics, whereas in other systems the data and clock paths may have a different set of timing characteristics.
Mismatch (or skew) between the data and clock paths may result in degraded setup and hold times. In modern high speed memory interface circuitry that uses double data rate (DDR) transfers (i.e., a data transmission scheme in which data toggles on both rising and falling edges of the clock), a small amount of skew will result in faulty data transfer during read/write operations. The clock that is used for transferring memory data is often referred to as the data strobe.
Conventional memory systems sometimes include circuitry for performing data strobe calibration during device startup (i.e., calibration operations for minimizing skew between the data and data strobe signals). During normal user operation, however, variations in the operating condition (i.e., voltage and temperature variations) can introduce random skew between the data and data strobe signals even after the startup calibration.